1. Field of the Invention
This invention relates to EPROM memory devices and more particularly to enhancement mode EPROM and flash EEPROM devices and method of fabrication of such devices.
2. Description of Related Art
Two level polysilicon cells with a split or overlapping gate electrode are generally known and used in a variety of applications.
EPROM (Erasable Programmable Read Only Memory) FET devices provide long term retention of charge to store data. The charge is stored on a floating gate electrode which is not electrically connected to a terminal. Instead, the charge is supplied to the floating gate electrode through an insulator. The data may be erased by exposure of the device to ultraviolet light to erase the stored data by discharging the floating gate electrode.
EEPROM (Electrically Erasable Programmable Read Only Memory) FET devices can be erased by electrical means instead of exposure to ultraviolet light.
Flash EPROM devices are EEPROM FET devices with a double gate electrode structure including a floating gate electrode and a control gate electrode. The device includes a tunnel oxide dielectric layer between the substrate and the floating gate electrode by a thickness of about 100 xc3x85 and an interelectrode dielectric layer about 200 xc3x85-250 xc3x85 thick composed of silicon oxide or ONO.
U.S. Pat. No. 4,313,253 of Henderson for xe2x80x9cMethod for Fabricating a Charge Transfer Channel Covered by a Stepped Insulating Layerxe2x80x9d shows a P-channel, split gate electrode memory cell having double level polysilicon cell with heavily doped polysilicon conductors with a gate oxide layer having a thickness between 300 xc3x85 and 500 xc3x85 thick. While Henderson, generally describes a double level polysilicon cell split gate electrode fabrication, the provision of a tunnel oxide layer suitable for the type of Fowler-Nordheim tunneling employed in EPROM devices is not suggested.
U.S. Pat. No. 4,646,425 of Owens et al., xe2x80x9cMethod for Making a Self-Aligned CMOS EPROM Wherein the EPROM Floating Gate and CMOS Gates are Made from One Polysilicon Layerxe2x80x9d shows an EPROM device with floating gate electrode and control gate electrodes which are formed of N+ doped polysilicon. The gate electrodes of the N-channel EPROM device are formed over a P-substrate and a gate oxide layer.
U.S. Pat. No. 5,198,380 of Harari for xe2x80x9cMethod of Making a Highly Compact EPROM and Flash EEPROM Devicesxe2x80x9d and U.S. patent No. 5,268,318 of Harari for xe2x80x9cHighly Compact EPROM and Flash EPROM Devicesxe2x80x9d describe N-channel EPROM and Flash EEPRQM devices with floating gate electrodes and control gate electrodes composed of heavily N+ doped polysilicon, with the caveat that the control gate electrode can be a silicide.
U.S. Pat. No. 4,816,883 of Baldi for xe2x80x9cNonvolatile Semiconductor Memory Devicexe2x80x9d describes an N-channel device (in FIG. 13 thereof) of the kind seen in FIG. 3A herein without any description of what doping is applied to the polysilicon conductors. Baldi also shows (in FIG. 1 thereof) an N-channel EPROM device of the kind seen in FIG. 3A herein with a doped polysilicon floating gate electrode and control gate electrodes without any description of what doping is applied to the polysilicon conductors.
Overall, two level polysilicon cells with a split or overlapping gate electrode are generally known and used in a variety of applications.
P-channel EEPROM and Flash EPROM devices are prone to being depleted after CHE (Channel Hot Electron) injection.
The cell of Henderson U.S. Pat. No. 4,313, 253 differs from the invention in the location of the sources and drains and function of the cell among other things.
This invention provides high speed, low voltages, low power consumption and less gate electrode disturbance.
The problem solved by this invention is to turn a P-channel nonvolatile device into an enhancement mode device which has advantages in circuit applications. Advantages of the P channel flash EPROM are as follows:
Hot electron injection current in P-channel flash EEPROM cell can be two orders of magnitude greater than in N-channel cell, while the channel current during programming in P-channel cell is two orders of magnitude less than in an N-channel cell.
In a split gate flash EEPROM device, the split gate flash EEPROM cell can be modelled as two transistors one of which is a programmable transistor with floating gate and a control gate in which there is a lower drain voltage, and there is no issue of overerasure.
The devices operate at high speed with low voltages, low power consumption and less gate electrode disturbance.
Some objects of this invention are as follows:
1. To combine P-channel nonvolatile and split-gate electrode Flash EPROM together.
2. Methods for solving the depletion issue in P-channel EEPROM and Flash EPROM and to increase the CHE injection in split-gate electrode Flash EPROM.
The present invention turns P-channel nonvolatile devices into enhancement mode which are more appropriate for circuit applications.
In accordance with this invention a method is provided for forming an FET semiconductor device, such as a flash EEPROM or a split gate device, in a doped silicon semi-conductor substrate having a surface, the substrate being doped with a N type of dopant. The method includes the steps of forming a tunnel oxide layer over the substrate, forming a floating gate electrode layer including a layer of N+ doped polysilicon over the tunnel oxide layer, forming an interelectrode dielectric layer over the floating gate electrode, and forming a control gate electrode including a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. Then follow the steps of patterning the tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode into a gate electrode stack, and ion implanting a source region and a drain region in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack of the split gate FET semiconductor device. Preferably, the floating gate has a thickness from about 1,000 xc3x85 to about 1,200 xc3x85.
It is also preferred that the floating gate electrode layer is a laminated structure comprising a lower polysilicon layer having a thickness from about 1,000 xc3x85 to about 1,200 xc3x85; an N+ doped polysilicon layer formed on the lower polysilicon layer having a thickness from about 1,000 xc3x85 to about 1,200 xc3x85, and an upper polysilicon layer having a thickness from about 2,000 xc3x85 to about 3,000 xc3x85. The tunnel oxide layer has a thickness from about 90 xc3x85 to about 100 xc3x85; and the source/drain dopant comprises P type dopant ions of boron fluoride, BF2, ion-implanted at an energy from about 30 keV to about 60 keV with a dose from about 1 E 15 ions/cm2 to about 5 E 15 ions/cm2. The substrate was doped by N type dopant comprising ions of phosphorus, P, ion-implanted at an energy from about 70 keV to about 100 keV with a dose from about 7 E 12 ions/cm2 to about 1.4 E 13 ions/cm2.
A device in accordance with this invention comprises a split gate FET semiconductor device formed on a doped silicon semiconductor substrate having a surface, the substrate being doped with a N type of dopant, the device having a channel, the channel having a channel width, a tunnel oxide layer over the substrate, a floating gate electrode layer including a layer of N+ doped polysilicon over the tunnel oxide layer, patterning the floating gate electrode layer into a split gate floating gate electrode have a narrower width than the channel width, an interelectrode dielectric layer over the floating gate electrode and the exposed portion of the tunnel oxide, a control gate electrode including a layer composed of P+ doped polysilicon over the interelectrode dielectric layer, patterning the tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode into a gate electrode stack above the channel, and ion implanting a source region and a drain region in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack. The floating gate has a thickness from about 1,000 xc3x85 to about 1,200 xc3x85.
Preferably, the floating gate electrode layer is a laminated structure comprises a lower polysilicon layer having a thickness from about 1,000 xc3x85 to about 1,200xc3x85, an N+ doped polysilicon layer formed on the lower polysilicon layer having a thickness from about 1,000 xc3x85 to about 1,200 xc3x85, and an upper polysilicon layer having a thickness from about 2,000 xc3x85 to about 3,000 xc3x85. The tunnel oxide layer has a thickness from about 90 xc3x85 to about 100 xc3x85, and the source/drain dopant comprises P type dopant atoms of boron fluoride, BF2, with a concentration from about 1 E 18 atoms/cm3 to about 1 E 20 atoms/cm3. The substrate is doped by N type dopant comprising atoms of phosphorus, P, with a concentration from about 1 E 16 atoms/cm3 to about 5 E 17 atoms/cm3.